In a conventional semiconductor device or semiconductor system having a ΔΣ modulator, a microcomputer or the like confirms an overflow detection signal outputted from a ΔΣ modulator and resets the internal state of the ΔΣ modulator, thereby to restore the ΔΣ modulator from its oscillation state (for example, refer to Patent Document 1).
Hereinafter, a conventional semiconductor device having a ΔΣ modulator will be described.
FIG. 19 is a block diagram illustrating the configuration of a conventional semiconductor device having a ΔΣ A/D converter.
The conventional semiconductor device includes a ΔΣ A/D converter 100 which converts input analog data A into digital data B, and a microcomputer 101 which confirms an overflow detection signal C outputted from the ΔΣ A/D converter 100, and issues a command of ΔΣ A/D converter soft reset setting D for resetting the ΔΣ A/D converter 100.
When the ΔΣ A/D converter 100 performs ΔΣ conversion of second order or more with integrators being cascade-connected, the internal state of the circuit might be oscillated in response to a large input signal or an input signal which steeply varies in steps. Once such oscillation occurs in the ΔΣ A/D converter 100, its amplitude is gradually increased, and circuit elements such as an operation amplifier which are driven by a limited power supply voltage become incapable of performing linear normal operation to lose operation accuracy, and thereby the ΔΣ A/D converter 100 becomes incapable of performing normal A/D conversion. Even when the input signal returns to the normal value after the start of oscillation, the ΔΣ A/D converter 100 might continue the oscillation. In this case, it is necessary to detect the oscillation and reset the internal state of the ΔΣ A/D converter 100. For this purpose, the ΔΣ A/D converter 100 is configured so as to compare the output of the integrator with a predetermined comparator threshold value, and output an overflow detection signal C to the microcomputer 101 to inform that overflow occurs in the ΔΣ A/D converter 100. The microcomputer 101 confirms the overflow detection signal C, and transfers a ΔΣ A/D converter soft reset setting D when overflow occurs in the ΔΣ A/D converter 100, thereby to reset the internal state of the ΔΣ A/D converter 100 and restore the A/D converter 100 from the oscillation state.
Patent Document 1: Japanese Patent No. 3192256
Patent Document 2: Specification of U.S. Ser. No. 5,012,244